A number of Flash Memory products exist today. They can be divided into two categories, the high-density components, mainly used for mass storage, and the high speed products, used for operational data storage. The Non-volatile field can be hence sub-divided in terms of the technology as the NOR implementation which is mainly good for very fast random access with execute in place capability, and the NAND implementation which is typically accessed in a serial mode, for program and read of large chunks of data at a time, that is suitable for high-density storage. Today the NOR and NAND memories share the market, with the NOR being larger in volume. The NAND memories are denser and the market for it has been growing at a faster pace than any other types of memories. Related Memories include architectural variations on the NAND memory interconnections for program and access using existing cell structures. This disclosure is a storage element and cell structure that can be used under different architectures by the people conversant with NAND and NOR memories, but it will be described using the well known and standard NAND structure for simplicity and understanding.
The NAND implementation is characterized by its capability to store and move large chunks of data, which can be accessed using a serial interface. In a typical NAND cell, area per storage bit is smaller than that for the NOR cell, as the NAND consists of multiple storage elements connected in series in the form of a NAND string which is in series with a drain select gate and a source select gate between two contacts. Typical number of storage elements in the NAND string has increased to 32 or more elements per cell. These elements in a cell are isolated from the rest of the cells that are connected to a bit line and the common source connection by The two select devices one at the drain end (drain select), between the drain contact and its nearest (the first) storage element, and another at the source end (source select) between the source contact and its nearest (the last) storage element in the string The interlink between the select devices and the storage elements and between the storage elements in a string is by a connective diffusion (the connect diffusion).
The program and erase functions of a typical NAND structure is by FN Tunneling between the floating gate and the memory well using voltages of 18 to 22V. This requires that devices that can withstand High voltage be used, in the peripheral circutry. The use of these high voltage devices, impact the speeds and make the devices slow. They also are large devices to prevent punch through with larger spacing between devices to avoid breakdown and leakage, thereby making the chip larger and more costly to manufacture.
Prior Art
FIG. 1 shows a typical prior art NAND memory structure. B1 to B4 are memory elements connected in series in a NAND string. A1 is a drain select device and A2 is a source select device. The drain diffusion (2) with the drain contact is separated from the nearest (first) memory element B1 by the Drain select device A1. Similarly the source diffusion (2x) and source connection are separated from the nearest (last) memory element B4, by the Source select device A2. The connect diffusions (7) link the memory element to the Source select and Drain select devices and to each other to provide an integrated series conductive path from source to drain in the cell when the select devices and the memory elements are in the “on” condition. The typical NAND cell in FIG. 1 is formed in a P-well (1) and comprise of N-channel elements and devices. The memory element of the prior art NAND cell is typically a channel region (8) controlled by the storage element (Bn), where ‘n’ is the number of the storage element (1 to 4) in FIG. 1. The storage element comprise, a stack etched floating gate poly silicon (12) separated from the channel (8) by a thin tunnel oxide (10), a control gate (14) that also acts as a word line over laying the floating gate and coupling to it through an inter-poly dielectric or protection oxide (13), as is well known and used in the Non-volatile memory cells. The NAND string or series connected storage elements B1 to B4 in FIG. 1 are isolated from the word line drain contact diffusion (2) and source line diffusion (2x) by the drain select device A1, and the source select device A2. A1 isolates the first connect diffusion (7) from the drain (2) by having a select channel (4) controlled by poly-silicon select gate (6) over laying a gate oxide (5). Similarly A2 isolates the last connect diffusion (7) from the source (2x) by having a select channel (4x) controlled by poly-silicon select gate (6x) over laying a gate oxide (5x). An integrated and interconnected channel can be formed by the diffusions (7) the channel regions (8) under the storage elements (B1 to B4), the channel regions under the select devices (4 and 4x) connecting the drain diffusion (2) to source diffusion (2x) in each storage cell.
In a memory, the cells are arranged in columns, each column having a bit line that connects all the drains of the cells in a column together. The source is common and connected together typically by a diffusion running in a direction perpendicular to the bit line and parallel to the word direction. The columns are then arranged together to form an array as will be well known to those who are involved in the art of memory. Every row of elements in an array is interconnected, in a direction perpendicular to the bit line direction, that is, the in a row direction, by the control gate that form the word line. The drain select lines and the source select lines are also interconnected in the row direction in the array providing selection capability to a row of cells in the array. The formation of the array and its various interconnection methods are well known to practitioners in the industry. NAND arrays are erased as a block of cells, that is, a number of pages of elements in one or more rows of cells. In a typical NAND array each column of cells has one or more data registers attached to the bit line. The data is loaded in serial fashion into, and also read from, these data registers. The data is then transferred in parallel to the set of elements selected (a typical page of data at a time) during program. Similarly data from a set of elements selected for read are transferred in parallel into the registers for serial read out during read operation.
A typical memory array (referred at times as bulk) comprise of all blocks of memory where a typical block comprise a group of cells with elements distributed and connected along the rows by the word lines. Typically each word line interconnects elements in a row to form a page of memory. Blocks can be one or more cells in depth along the column though a typical block is a cell in depth. The bulk is the entire memory array comprising of all the cell blocks. It should be noted that there are different ways of interconnecting the elements and cells in an array. Those who are conversant with memories and their architectures will know the different interconnection modes within the array.
The typical write operation of a prior art NAND cell, comprise both the erase operation where by the electron charge is removed, are by Fouler-Nordheim Tunneling (FN Tunneling) in a block or bulk mode, and the program operation, where by electrons are stored in the floating gate. The first operation is typically the erase operation when the electron charge in the floating gates of the storage elements are removed. This is done by generating a voltage gradient of sufficient magnitude across the tunnel oxides (10) of the storage elements to remove electrons from the floating gate (12), by high voltage gradient of the right polarity applied between the control gate (14), that will be coupled down to the floating gate from the control gate, and the well (1) to appear across the floating gate oxide. The necessary field across the tunnel oxide to achieve erase can be induced in three ways: 1) by applying a high negative voltage (−Vpp) to the control gate with the well at ‘0’V, 2) by applying a lower negative voltage (approx. −½ Vpp) to the control gate and applying a positive voltage (approx. ½ Vpp) to the well, or 3) by applying a high positive voltage (Vpp) to the well while keeping the control gates at ‘0’ potential. Of these the most common is to apply high voltage to the well with control gate at ‘0’ potential for erase. This mode of erase is non selective and the memory cells are erased as a block (group of cells in a row or multiple rows in a specific well) or bulk (all cells on chip), based on the applied voltage on the control gate and the well.
Typically program is the selective operation and it is done on a page (all storage elements along a row or word line) level. The data which may be ‘1’ or ‘0’ is loaded into a set of registers serially and then presented to the cells through the bit lines, the lines connecting the drains of all the devices in a column of the array. Typically a self boost scheme is employed to write a ‘1’, that is leave the selected storage element, on the selected word line in the erased state while a ‘0’ allows programming of the selected storage element.
Assume that the data register is loaded with a ‘0’ indicating that the element in the cell needs to get programmed. The ‘0’ loaded in the register keeps the bit line connected to it and hence the drain diffusions (2) in the column of cells connected to the bit line at ground ‘0’ potential. The gate (6) of the Drain select transistor (A1) of the selected row of cells is pulled to value approx. equal to Vdd, during write, turning on the drain select device. The source select transistor (A2) is kept in the off condition by keeping the gate (6x) of that device at ground or ‘0’ potential. The unselected word lines in the selected cell are kept at an intermediate high voltage close to half the programming voltage (Vpp/2). This turns on the channel (8) of unselected storage elements by the application of the voltage (½ Vpp) to the control gates (14) of the storage elements connected to the unselected word lines. The coupled down voltage to the floating gates (12) of the unselected storage elements, is not sufficient to cause tunneling across the tunnel oxide (10) between the floating gate and the channel (8), even though the channel is at ground potential. The selected word line is pulled up to the full programming voltage (Vpp). This provides the high voltage (Vpp) to the control gate (14) of the selected storage element. This voltage applied is sufficient, as the channel (8) of the selected element is at ground or ‘0’ potential, to produce a coupled down voltage on the floating gate (12) of the selected storage element, if the channel is at ground potential, to provide sufficient potential gradient across the tunnel oxide (10) between the floating gate (12) and the channel (8) of the selected storage element, to cause tunneling of carriers across the tunnel oxide (10) and accumulation of charge in the floating gate from the channel. Since the select gate (6) for drain select transistor is approx. at Vdd and the bit line connected to the drain (2) is at ground, and all the series storage elements in that selected cell are fully on, the ground voltage from the bit line appears in the channel under the selected element, and hence cause programming of the element. This programming process does not generate a current flow in the cell, other than that required to charge the capacitors and program the storage element, in fact it is a very low power programming process.
Now if the register connected to the bit line is loaded with a ‘1’, that is a value close to Vdd, when the word lines in the selected cell is pulled up, the unselected word lines to approx. Vpp/2 and selected word line to Vpp, similar to the case explained earlier, the floating gates in the cell has a coupled up voltage which in turn tries to pull up the channel voltage by capacitive coupling. If the channel voltage is not actively pulled to ground as in the earlier case, but is allowed to rise to a value close to Vdd value, the drain select device of the selected cell, by virtue of having its gate (6), its drain diffusion (2) and its source diffusion, which is the first connect diffusion (7) all at a voltage close to Vdd, is shut off and the channel remains free to float to a value of voltage dictated by the capacitive coupling limited by the leakages. This causes the integrated channel {all the connect diffusions (7) and the channels beneath the storage devices (8)} to be pulled up to a value high enough by the coupled voltage to prevent the potential gradient across the tunnel oxide (10) of the selected storage element from reaching a value sufficient to generate a potential gradient across the tunnel oxide for tunneling to take place. This in turn result in the selected storage element being left erased. Thus the data stored in the selected storage element is directly related to the information stored in the register connected to the related bit line. In a NAND cell this program operation is done for storage elements connected to a single word line in a row of selected cells at a time and is called page program.
Read back of the data is accomplished by checking the status of the storage element using a sense circuit and hence getting the data back and it is well known in the industry. Multiple sense schemes are available for sensing and retrieving the data stored in the storage elements of the cell. Typically the read back is also done for an entire page at a time and data stored in page register and is serially streamed out from these registers.
It has been shown that the thickness of the tunnel oxide is of the order of 70A and cannot be scaled without impacting the reliability and disturb characteristics of the elements. In order to cause tunneling typical potential gradient of 10 MeV/cm is necessary, that is a voltage of over 7 V applied across the tunnel oxide is essential to initiate tunneling with the 70A oxide. The prior art NAND cells use the stack etch technology to self align the control gate and the floating gate. This provides a three-sided coverage of the floating gate by the control gate. The coupling between the control gate and the floating gate of the storage element is typically of the order of 45-50%. This means that only about half the voltage applied to the control gate is coupled down to the floating gate to appear across the tunnel oxide. This in turn mandates relatively high voltage Vpp use during program and erase operations. In order to improve this coupling ONO, an Oxide-Nitride-Oxide sandwich inter-poly dielectric, with a Nitride inter-layer that has a higher dielectric constant than oxide, has been used in the prior art. This ONO process adds to the mask count and process complexity and hence the cost of the memory. In return it reduces the high voltage requirement of the cell marginally by increasing the coupling to around 60%. The ONO introduces problems of retention as the Nitride itself conducts charge through hopping conduction that is well known in the industry. The use of the two oxide layers on top and bottom of the Nitride of sufficient thickness is to prevent this leakage, which in turn increase the thickness of the inter-poly dielectric and hence reduce the coupling and the ability to scale. It should be noted that if the coupling ratio of the NAND Storage element, that is the ratio of the coupling between the control gate and floating gate as against the total coupling to the floating gate from all sides is low, only that amount of the applied voltage to the control gate appear on the floating gate. This also means that voltage gradient due to Vpp (1-the coupling ratio) appear across the inter-poly dielectric, causing stress to that dielectric increasing the leakage through the dielectric ONO layer.
The Nitride layers are also prone to accumulation of charge by trapping in the layer. At high voltages used in the program and erase process of the prior art cell, the Inter-layer dielectric is subject to high potential gradients. These are usually sufficient to cause charge transport through the layer and hence trapping. This trapped charge will cause accelerated window closing during write cycling and reduce the reliability of the cell in operation.
The leakage characteristics and the charge trapping characteristics of the ONO are made worse under high temperature and high voltage conditions and impact the high temperature characteristics of the storage element, typically making it less suitable for high temperature operation in industrial and automotive applications.
Another problem that has been identified in the prior art cells as the technology shrinks is the problem of coupling of the floating gate to adjacent memory elements through the open sides of the floating gates. This can result in voltage swings in the cell that are not designed in and controlled.
All these results in problems of cell disturb and problems of data retention in the memory cells.
Another problem is the encroachment of the connect diffusion under the tunnel oxide. This has the effect of reducing the reliability of the cell by making a high doped region with its field regions to be under the tunnel oxide and the floating gate thereby changing the uniformity of tunneling from the channel. This can reduce the program-erase or write cycling characteristics of the memory elements by localized degradation. This also has an impact on the high temperature characteristics of the cells and retention characteristics of the cell due to generation-recombination in the depletion region resulting in collection of charge by the floating gate.
Some of the problems of the typical present day NAND flash cell are:    1. Very high Voltage program and erase operation.    2. Low coupling resulting in increased stress on the inter-poly dielectric.    3. Lack of ability to scale vertically the inter-poly dielectric.    4. Lack of ability to scale without being affected by coupling to neighboring cells.    5. Need for sophisticated program erase controls to prevent over programming and over erase.    6. Full processor controlled reliability screening and redundancy due the cells being prone to disturb conditions.    7. Frequent checks and error correction methods are needed to ensure that the cells retain the data.    8. Reduced high temperature capability (typical commodity operation).    9. Reduced data retention.    10. Reduced program erase cycling.    11. Difficult to scale devices with technology node without impacting performance due to punch trough.    12. Process complexity increases with ONO.
What is Proposed
What is proposed is a cell and technology to be used in a NAND memory array. Three separate modifications/improvements are proposed, that improve the operation, the operating temperature range and increase the reliability, both retention and endurance, of the cell. The first modification (modification 1) is one that uses a five side overlapping control gate, to improve coupling ratio with associated reduction in the program and erase voltages, and elimination of unwanted disturb conditions due influence of the neighboring cell through coupling to the floating gate. The high coupling ratio reduces the stress on the inter-poly dielectric and hence improves retention and endurance characteristics. The second modification (modification 2) is by using the five side overlapping control gate structure to space away the diffusion edge from the floating gate and providing a pair of side select gates in parallel with the floating gate, on either side of the floating gate, to eliminate the variations in the field due to high doping in the channel and hence improve the uniformity of tunneling from the channel through the tunnel oxide. This improvement moves the high field depletion regions where electron hole pair generation takes place, especially with increased temperature, away from the floating gate, there by improving the operating temperature range of the devices. This improvement also improves the endurance and data retention characteristics of the cell by improving the uniformity of current flow through the tunnel oxide and hence reducing the damage to the oxide. The use of the five side coverage of the floating gate with the improvement in coupling ratio provide a third improvement, (modification 3) that is the ability to use high quality grown or deposited oxide or a combination of the two oxides as inter-poly dielectric instead of ONO. The increased coupling ratio also allows reduction in the inter-poly oxide thickness as the voltage appearing across it is reduced. FIG. 2 is a first implementation of some of the proposed embodiment with the modification 1 that provides the five side coverage of the floating gate by the control gate, and FIG. 3 is the preferred implementation with modifications 1 and 2. Modification 3 can be implemented in both implementations shown in FIG. 2 and FIG. 3, as both have high coupling ratios due to the coverage and low inter-poly voltage drop. Use of Oxide as the inter-poly dielectric brings with it some additional advantages. First is the simplification of the manufacturing process due to the elimination of steps needed for ONO processing. Second is the improvement of retention characteristics of the cells due to elimination of charge leakage by hopping conduction through the Nitride. Third is the improvement in write cycling reliability, by the reduction of window closing effect due to charge trapping in the Nitride of the ONO.
The cell architected is not for high-density and is not the smallest NAND cell, instead it has been architected for improved manufacturability, quality and reliability. The disturb conditions have been eliminated by cell and array design and retention and endurance (write cycling) characteristics are improved. This cell will also be much more manufaturable and yieldable as ONO issues are eliminated and lower voltages are used to program and erase. The use of the side select gates of the embodiment in FIG. 3 enable the cells to be in depletion or enhancement during operation.
Some of the advantages of the proposed cell are:    1. A lower program erase voltage is used as compared to the existing NAND structures at the same node due to the improved coupling ratio from 50 to 80%.    2. Eliminates the need for ONO and allows the use of Oxide as inter-poly dielectric, making the element easier to manufacture and more robust.    3. The cell with side select gates is immune to over erase problems.    4. Eliminates the unwanted coupling from adjacent cells to the floating gate.    5. The lower Program-erase voltage reduces the stress on the inter poly oxides and hence increases the reliability of the cell.    6. Provides cells that are capable of high temperature operation by moving the junction depletions, where thermal generation and acceleration take place, away from under the floating gate.    7. Very high retention is achieved due to low and uniform tunnel currents by elimination of junction depletion overlap of floating gate.